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Computer Organization and Architecture

Logic Gates

Circuits to Truth Tables

Circuits to Expressions

Expressions to Circuits

Finding SOP from K-Map

Finding POS from K-Map

Finding SOP from K-Map having Don't Care

Half Adders

Full Adders

Flip Flop

Integrated Circuits

Decoders

Multiplexers

Registers

Counters

RAM

ROM

Number Systems

Complements

Number Representations

Binary Addition and Subtraction

Gray Codes

Error Detection Codes

Register Transfer Language

Bus and Memory Transfers

Arithmetic Micro-operations

Logical Micro-operations

Shift Micro-operations

Basic Computer Organization

Timing and Control

Instruction Cycle

Instruction Types

Interrupt Cycle

Complete Computer Description

General Register Organization

Stack Organization

Evaluation of Arithmetic Operations

Address Modes

Instruction Formats

RISC and CISC Architectures

Parallel Processing

Multiplication Algorithms

Logic Gates

Circuits to Truth Tables

Circuits to Expressions

Expressions to Circuits

Finding SOP from K-Map

Finding POS from K-Map

Finding SOP from K-Map having Don't Care

Half Adders

Full Adders

Flip Flop

Integrated Circuits

Decoders

Multiplexers

Registers

Counters

RAM

ROM

Number Systems

Complements

Number Representations

Binary Addition and Subtraction

Gray Codes

Error Detection Codes

Register Transfer Language

Bus and Memory Transfers

Arithmetic Micro-operations

Logical Micro-operations

Shift Micro-operations

Basic Computer Organization

Timing and Control

Instruction Cycle

Instruction Types

Interrupt Cycle

Complete Computer Description

General Register Organization

Stack Organization

Evaluation of Arithmetic Operations

Address Modes

Instruction Formats

RISC and CISC Architectures

Parallel Processing

Multiplication Algorithms

Whenever a message is transmitted, it may get scrambled by noise or data may get corrupted. To avoid this, we use error-detecting codes which are additional data added to a given digital message to help us detect if an error occurred during transmission of the message. A simple example of error-detecting code is **parity code**.

Parity code is nothing but a single bit code that is added to the original bit stream (original data) in order to make the total count of 1's either ODD or EVEN. Due to this mechanism, entire parity code system is categorized into the following two types:

- Odd Parity: In order to make count of 1's ODD.
- Even Parity: In order to make count of 1's EVEN.

The following table shows both the EVEN Parity and ODD Parity bits for a 3-bit data-word:

Following diagram shows how parity mechanism works for detecting one bit error in a three bit data. The count of 1 in original data was even, we appended an additional 1 to make the count of ones ODD. On the receiver's end, count of 1 was found even. This shows there is error in the received data.

Parity Generator Circuit uses a combination of nested XOR and XNOR gates to compute the ODD Parity bit while Parity Checker Circuit uses the same combination on the receiver's end to check for that ODD Parity.

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