RISC and CISC Architectures

RISC (Reduced Instruction Set Computer):

RISC Architecture was introduced in 1980s when instruction sets were rather easy to decode and execute. The easyness was due to several design level artifacts. At that time hardware was not much capable to process complex instructions hence even complex instructions were to be handled by dividing into many smaller and easier instructions.

Following are the key properties of RISC Computers:

1. Relatively Few instructions per process.
2. Relatively few addressing modes.
3. Memory Access limited to LOAD and STORE.
4. All operations are performed within CPU registers.
5. Fixed length easily decodable instructions.
6. Single Cycle Instruction Execution.
7. Hardwired rather than Microprogrammed.

CISC (Complex Instruction Set Computer):

CISC architecture came later to RISC. The main reason was increasing capabilities of modern softwares. To handle such complexity instructions must be complex. An instruction set with simpler instructions will make a huge lot of instructions for handling of complex softwares. Hence better is to choose complex instruction set. The development of ICs in recent years has helped developers work efficiently on CISC architectures.

Following are the key properties of CISC Computers:

1. Large number of instructions per process.
2. Large variety of addressing modes.
3. Varriable length instruction formats.
4. Memory access is such frequent that operands are manipulated in memory.
5. Multi-cycle Instruction Execution.
6. Control is often microprogrammed.