Instruction Cycle

Instruction Cycle is a detailed procedure using which, an instruction triggers and completes its execution. Usually a computer works with 16-bit instruction code which is further divided into 3 significant parts- the Mode Bit, the Opcode and the Address of operand. Each of these parts must be decoded by the control unit so that the execution can take place. The entire procedure is divided into following three phases-

1. Fetch Phase
2. Decode Phase
3. Execute Phase

Fetch Phase:

Fetch phase refers to the extraction of a new instruction from memory to the Instruction Register (IR). For this to occur, the memory address of the instruction is transfered into Program Counter (PC) by the control unit. PC then transfers the address to Adress Register (AR). AR now explores the memory and extracts the instruction. The extracted instruction is transfered to IR and PC gets an increment of 1. Increment of PC refers to the subsequent pointing towards the next instruction in memory. Consider the following RTL notations-

Decode Phase:

Decode phase starts after instruction is stored in IR. The first thing to decode is Mode Bit. It is transfered in a separate flip-flop I. Next is to decode the 3-bit Opcode which is done using a 3 to 8 decoder. D₇output of the decoder is- when 1, denotes that the opcode was 111. Thus the decoder output along with I flip-flop determine whether the instruction was a Memory Ref. Instruction or not. In concurrence, the 12 bit Operand address is transfered into AR so that the operand can be fetched out of memory. Consider the RTL notations-

Execute Phase:

Execute phase starts after the instruction is decoded completely. The operand is fetched out from memory during this phase and rest of the process is accomplished by arithmetic and logic circuits. Fetching of operands depend upon the mode of address being used in the instruction.

Flowchart showing Instruction Cycle: